1. Field of the Invention
The present invention relates to a circuit for controlling a refresh oscillator, and more specifically, to a circuit for controlling a refresh oscillator, wherein refresh characteristics can be tested in a more efficient manner in such a manner that the refresh characteristics are tested at a refresh cycle, which is extended as long as a predetermined time from an originally set refresh cycle, in a user test mode so as to measure a refresh margin over a wide temperature range.
2. Discussion of Related Art
In DRAM devices, stored data are lost after a predetermined time elapses. In order to guarantee data retention characteristics, an operation of refreshing the stored data by activating a bit line sense amplifier is performed. In order to guarantee the operating cycle of self refresh, wherein the refresh operation is automatically repeated after a predetermined time elapses during the refresh operation, a self-refresh oscillator is used. The self-refresh oscillator generates a signal of a given cycle, and uses the signal to decide a self-refresh cycle.
Meanwhile, DRAM devices undergo a variety of tests at a wafer and package level so as to determine whether they meet AC/DC specifications of a product in the process of mass production. Of them, the refresh characteristic test is very important, test methods for various refresh characteristics have been used. More particularly, in case of a low-power DRAM used for mobile products, etc. a temperature compensation self refresh (TCSR) method in which the refresh current is reduced with different refresh cycles depending upon temperature characteristics is used. In a wide temperature range, refresh characteristics have to be tested. Accordingly, in order to change the refresh cycle according to temperature, an oscillator whose cycle is changed according to temperature, a method of controlling the division number, and the like have been employed.
FIG. 17 shows a circuit for controlling the refresh oscillator in the prior art.
An oscillation signal generation circuit 11 generates an oscillation signal OSC depending upon a basic refresh cycle if a refresh signal SRF is generated according to an externally applied refresh command. The oscillation signal OSC is output with its level changed on the basis of an internal signal delay time within the oscillation signal generation circuit 11 as a cycle. A reset circuit 12 uses a refresh signal SRF and a refresh cycle signal PSRF to output a delay signal SRFDD, a first reset signal CRST and a second reset signal ORST being a refresh signal. Whenever the refresh signal SRF is applied as a high level and the refresh cycle signal PSRF is applied as a pulse of a high level, the reset circuit 12 outputs the first reset signal CRST and the second reset signal ORST of a high level. At this time, the first reset signal CRST initializes a divider circuit 14, and the second reset signal CRST initializes the oscillation signal generation circuit 11.
A clock signal generation circuit 13 generates a signal JDG having the same phase as that of the oscillation signal OSC and a clock signal CLK having an opposite phase to that of the oscillation signal OSC according to the refresh signal SRF and the oscillation signal OSC.
The divider circuit 14 is initialized according to the first reset signal CRST, and generates divider signals RCA<0:3> that are increased depending upon dividers 14a to 14d according to clock signals CLK. For example, a first divider 14a can output the divider signal RCA<0> of one cycle according to two cycles of the clock signal CLK. A second divider 14b can output the divider signal RCA<1> of one cycle according to two cycles of the output signal RCA<0> of the first divider 14a. 
A fuse set circuit 15 consists of a fuse. It outputs a plurality of fuse signals FUS<0:3> for deciding the refresh cycle depending upon a power-up signal PUPB and a cutting state of the fuse. For example, when the fuse signal FUS<0> is a high level, the refresh cycle is set to 1 division. When the fuse signal FUS<1> is a high level, the refresh cycle is set to 2 division. When the fuse signal FUS<2> is a high level, the refresh cycle is set to 4 division. When the fuse signal FUS<3> is a high level, the refresh cycle is set to 8 division. A greater number of divisions can be set according to an output combination of the fuse signals FUS<0:3>.
A refresh cycle signal generation circuit 16 compares the divider signals RCA<0:3> and the output signals FUS<0:3> of the fuse set circuit according to a delayed refresh signal SREDD. If the divider signals RCA<0:3> and the output signals FUS<0:3> of the adder are identical to each other, a refresh cycle signal PSRF is output as a high level at a rising edge of the signal JDG.
However, the refresh cycle is not always constant, but has some variation in width depending upon variation in a process condition, an operating voltage and temperature. FIG. 15 shows a refresh time of a chip depending upon variation in temperature. The refresh time has an inverse proportion to temperature, i.e., the higher temperature, the greater the refresh time tREF. At this time, tREFM is the refresh time of a chip, and refers to the characteristics of the chip. As indicated by A in FIG. 15, in the case where refresh is performed at a cycle of tREF=OSC1, there is no problem in refresh since the cycle is shorter than that of tREFM. In the event that refresh is performed at a cycle of tREF=OSC2 as indicated by B in FIG. 5, a chip can be passed or failed depending upon variation in the cycle of an oscillator because the refresh time is some of the characteristic value of the chip. Accordingly, in order to prevent problems from occurring, it is necessary to test refresh characteristics with sufficient margin by predicting change in a refresh cycle depending upon variation in process condition, operating voltage, temperature, etc. of a chip in the case where the refresh characteristic is tested.